Method and system for designing circuit layout

ABSTRACT

A circuit layout design method capable of an LSI circuit or an electronic printed circuit board free of electromagnetic interference is provided. The layout design method according to the invention includes a quasi-stationary circuit reduction step of deviding an entire circuit represented by a net list and a part library into a plurality of quasi-stationary closed circuits having a reduced size so that an intensity of an electromagnetic wave radiated from each of the quasi-stationary closed circuits is not more than a predetermined value; a wiring constraint condition calculation step of calculating constraint conditions for each of wirings mutually connecting the plurality of quasi-stationary closed circuits so that the intensity of the electromagnetic wave radiated from each of the wirings is not more than the predetermined value; and a layout step of laying out parts and the wirings based on the net list and the parts library so as to satisfy the constraint conditions.

TECHNICAL FIELD

The present invention relates to a circuit layout design method and asystem for the circuit layout design method. More specifically, thepresent invention relates to a circuit layout design method for adigital printed circuit board and an LSI (large scale integrated)circuit on which high-speed, high-frequency circuit devices are mainlymounted.

BACKGROUND ART

As for the conventional digital circuit design system, an LSI circuitdesign system and a printed circuit board (PCB) circuit design systemhave existed independently of each other, and an integrated EDA(electronic design automation) system from the LSI to the PCB has notexisted.

In addition, in the process of the LSI design, no organic connection hasbeen established between process design and logic design and noconsistent integrated system has existed. Although information such asknow-how's have been provided to take measures against EMI(electromagnetic interference), no consideration has been given to suchan electromagnetic free design technique as to be able to beincorporated into the EDA design system.

Meanwhile, in relation to the printed circuit board circuit designsystem, a simplified design check tool such as an EMI rule checker hasexisted; however, no basic design rules have been established.

A conventional design technique in relation to a technique forsuppressing digital equipment electromagnetic interference will next bedescribed.

1. In designing a digital printed circuit board (PCB), a highly advancedEDA system is used mainly for the logic design. High-rate simulation ina design phase is targeted at logic and delay time.

2. In designing an LSI circuit, a lumped parameter system is responsiblefor design and analysis without any strict basis. In the lumpedparameter system, a lumped parameter-system simulator represented bySPICE (simulation program with integrated circuit emphasis) performsanalysis in relation to the electromagnetic interference.3. Conventionally, attention has been paid to signal wirings so as totackle electromagnetic interference problems. This is because the signalwirings occupy the most parts of the printed circuit board (PCB) or asemiconductor LSI and high-frequency current exists on the signalwirings. To this end, an electromagnetic radiation simulator whichsimulates electromagnetic radiation from the PCB including thesemiconductor LSI has been developed and put to practical use. However,the electromagnetic radiation simulator has a problem that the simulatedelectromagnetic radiation greatly differs from actually measuredradiation, and the cause of the problem has not been cleared up. On theother hand, thanks to a recent study, it has been discovered for thefirst time that the major cause of the electromagnetic radiation from adigital equipment lies in a power supply circuit. For example, it hasbeen discovered that it is possible to suppress electromagneticradiation over the entire frequency band by 5 dB or more only bychanging the power distribution of the PCB from conventional flat platepower distribution to wiring power distribution (see Japanese PatentLaid-Open Application Publication Nos. 9-139573 (to be referred to as“Document 1” hereinafter) and 11-40915 (to be referred to as “Document2” hereinafter)). In addition, a chip capacitor conventionally used as adecoupling capacitor has its own resonance frequency in a low frequencyband and has a problem of being incapable of following the speeding up.To solve this problem, a line component that decreases the impedance ofa power supply line to a high frequency range has been invented (seeJapanese Patent Laid-Open Application Publication No. 2001-119154 (to bereferred to as “Document 3” hereinafter).

DISCLOSURE OF INVENTION

The digitization of electronic equipment increasingly progresses. For alogic design region, which occupies large parts of electronic equipmentdesign, CAE (Computer Aided Engineering) design covering design throughmanufacturing widely spreads and greatly contributes to the improvementof the quality and efficiency of design and manufacturing. However, fora so-called electronic SI (Signal Integrity) region which occupies theremaining parts of the electronic equipment design and which includespackaging, structure, wiring and the like, there is a tendency to relyon the discretion of an engineer involved in design. As a result, anintegrated optimum design method for covering design throughmanufacturing has not been established. In light of the presentsituations, the conventional arts 1 and 2 (Documents 1 and 2) have thefollowing problems.

1. First, the conventional electromagnetic interference suppressiontechnique is in a field of trouble shooting. A highly advanced EDAsystem is used for the design of a digital printed circuit board (PCB)mainly in terms of the logic design. The simulation technique related toelectromagnetic interference is created in order that not an engineerinvolved in design but an engineer familiar with the electromagneticinterference uses the technique whenever a problem occurs. Therefore,the first problem with the conventional art is that it is substantiallyimpossible for a design-involved engineer who is not familiar withelectromagnetic interference problems to inspect electromagneticinterference in a design phase.2. Second, a lumped parameter system theory is applied to the LSIcircuit design and wave analysis cannot be performed based on thetheory. Inside the LSI is designed and analyzed using a lumped parametersystem without any strict basis, and analysis related to electromagneticinterference is also performed by a simulator of a lumped parametersystem represented by the SPICE. The simulator of this type has aproblem of being incapable of dealing with a current as a wave. It isestimated that the frequency of a circuit current including higherharmonics becomes high as compared with the size of a semiconductor LSIin the future. As a result, signals in the LSI and the power supplycurrent of the LSI are reaching a frequency range which may possiblytake on the character of waves. Due to this, it is increasinglynecessary to make designs and perform circuit simulation whileconsidering a current as a wave. This is the second problem with theconventional art.

It is, therefore, an object of the present invention to provide acircuit layout design method and a circuit layout design system capableof designing an LSI circuit and an electronic circuit board free ofelectromagnetic interference.

According to the present invention, there is provided a circuit layoutdesign method including: a quasi-stationary circuit reduction step ofdividing an entire circuit represented by a net list and a part libraryinto a plurality of quasi-stationary closed circuits having a reducedsize so that an intensity of an electromagnetic wave radiated from eachof the quasi-stationary closed circuits is not more than a predeterminedvalue; and a wiring constraint condition calculation step of calculatingconstraint conditions for wirings mutually connecting the plurality ofquasi-stationary closed circuits so that the intensity of theelectromagnetic wave radiated from each of the wirings is not more thana predetermined value.

The circuit layout design method may further include a layout step oflaying out parts and the wirings based on the net list and the partslibrary while keeping the constraint conditions.

In the circuit layout design method, the quasi-stationary circuitreduction step and the wiring constraint condition calculation step maybe executed for each of frequencies in a descending order and executedso that each of the quasi-stationary closed circuits for a certainfrequency includes one or more the quasi-stationary closed circuits fora higher frequency than the certain frequency.

In the circuit layout design method, the constraint conditions mayinclude at least a maximum wiring length.

In the circuit layout design method, the quasi-stationary circuitreduction step may include steps of: obtaining a current waveform by aSPICE (a simulation program with integrated circuit emphasis) using apower supply terminal model and one of an IBIS (I/O buffer informationspecification) model and an IMIC (I/O interface model for integratedcircuit) model; Fourier-transforming the current waveform to a currentspectrum; and calculating a field intensity spectrum at a distance bydipole antenna radiation or electromagnetic analysis using the currentspectrum.

The circuit layout design method may be used for layout design of aprinted circuit board.

The circuit layout design method may be used for layout design of asemiconductor device.

The circuit layout design method may be used for integrated design of asemiconductor device and a printed circuit board.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a conceptual view of the best mode embodiment of a circuitlayout design system according to the present invention;

FIG. 2 is a detailed block diagram of the best mode embodiment of thecircuit layout design system according to the present invention;

FIG. 3 is a pattern diagram showing one example of grouping an entireprinted circuit board (PCB) into quasi-stationary closed circuit (QSCC)blocks;

FIG. 4 is a pattern diagram showing examples of the QSCC block;

FIG. 5 is a pattern diagram showing one example of extending the minimumunit of the QSCC block to a functional block in an LSI;

FIG. 6 shows the concept of a design flow executed by the circuit layoutdesign system according to the present invention;

FIG. 7 is a flow chart showing an overall circuit layout design methodaccording to the present invention;

FIG. 8 is a flow chart showing the overall circuit design layout methodexecuted by a QSCC designer;

FIG. 9 shows one example of an electric field spectrum as a result ofelectromagnetic field analysis; and

FIG. 10 shows one example of a QSCC database.

BEST MODE FOR CARRYING OUT THE INVENTION

The outline of the present invention will first be described.

1. An EDA system incorporating therein an electromagnetic interferencesuppression function is developed, and a design environment capable ofdesigning a digital circuit having an electromagnetic interferencesuppression effect without being aware of electromagnetic interferencesuppression is established. A completely novel concept of aquasi-stationary closed circuit (QSCC) that the present invention newlyproposes is incorporated in the highly advanced EDA system centering onthe conventional logic design, whereby it is possible to design adigital printed circuit board and a semiconductor LSI free ofelectromagnetic interference. A simulator related to electromagneticinterference according to the present invention is used for real-timeinspection in a design phase and has the same function as that of alogic simulator for the conventional EDA system. The electromagneticinterference-related simulator developed from such viewpoints is noveland different from existing simulators. A database system plays animportant role in the system developed. This database system is createdbased on a completely new concept. The database consists of a QSCC and asignal/power supply line, and is created using detailed parameters ofsemiconductors and components through a novel dedicated tool. The QSCCis provided with an impedance source model per power supply terminal orsignal terminal as well as logic and physical interfaces. According tothe present invention, another invention filed by the applicant of thepresent application (Japanese Patent Laid-Open Application PublicationNo. 2001-222573 (to be referred to as “Document 4” hereinafter) isapplied to the power supply terminal model and an IBIS (I/O bufferinformation specification) already used for simulation or an IMIC (I/Ointerface model for integrated circuit) which is an improved IBIS isapplied to the signal terminal model.

The techniques disclosed in Document 4 will be summarized as follows.The technique of Document 4 relates to the power supply model of an EMIsimulation semiconductor integrated circuit, which model is targeted ata printed circuit board and a semiconductor integrated circuit. Thepower supply model comprises an inverter section to which power issupplied, and an equivalent internal capacitance section connectedbetween the output of this inverter section and the power supplythereof.

According to the technique of Document 4, the interior of the entire LSIis expressed in the form of transistor description. The technique ofDocument 4 is intended to simulate a radiation field generated on aprinted circuit board. The number of transistors which constitute thisLSI power supply model in the form of transistor description is farsmaller than the number of actually used transistors. The EMI simulatorobtains a power supply current carried through the printed wiring boardusing this model. This model is created by extracting sections that areoperating from the net list of the actual LSI, and, as described above,decreasing the number of transistors. In addition, the remainingsections that are not operating are simplified, thus creating an LSIpower supply model as a whole.

2. A new circuit design concept that a lumped parameter system isemployed in the QSCC and a distributed system is employed outside of theQSCC introduced into design and simulation for the first time. In theexample of the semiconductor circuit, the circuit current of each wiringin the semiconductor circuit is obtained by a simulator of a lumpedparameter system for each frequency, and the length of the wiring isrestricted so that the intensity of an electromagnetic wave radiatedfrom the wiring takes the value which can be substantially ignored. Inthis analysis, a two-dimensional or three-dimensional electromagneticsimulator is employed to obtain a maximum wiring length for each wiringstructure. If a closed circuit not larger than the wiring length thusrestricted is taken out, it can be considered that this closed circuitis one of the QSCCs and that an electromagnetically quasi-stationarystate is maintained in the closed circuit. Therefore, the simulator of alumped parameter system can be utilized to analyze the circuit in theQSCC without causing any problems. Further, as lower the frequency is,the larger the allowable wiring length becomes. Due to this, it ispossible to ensure applying a circuit theory of a lumped parametersystem to the interior of the QSCC in any case, although the allowablewiring length depends on the frequency of the circuit current. On theother hand, if a transmission line structure that is established in themicrowave engineering is used for wirings outside of the QSCC used forsignal distribution and power supply distribution, it is possible tosuppress electromagnetic radiation. Consequently, it is possible togreatly improve design efficiency and design quality.

To attain the above-stated object, the present invention incorporates acompletely new concept of the quasi-stationary closed circuit (QSCC)into design tools (such as a simulator and a layout CAD) for a digitalprinted circuit board and a semiconductor LSI.

The concept of the QSCC that the present invention proposes for thefirst time for design method free of an electromagnetic interference fordigital equipment will be described. Generally, if the wavelength λ of acircuit current is sufficiently large as compared with the size of aclosed circuit, electromagnetic radiation is eliminated. In other words,in order to realize a device free of mutual electromagnetic interferenceproblems, it is effective to design all closed circuits to havequasi-stationary states.

The embodiment of the present invention will next be described withreference to the accompanying drawings. FIG. 1 is a conceptual view ofthe best mode embodiment of a circuit layout design system according tothe present invention. This conceptual view includes main constituentelements which can be applied to both the semiconductor LSI design andthe circuit layout design. Referring to FIG. 1, the circuit layoutdesign system 1 consists of a QSCC database 2, a QSCC grouping &database extraction analysis tool (to be referred to as “QSCC designer”hereinafter) 3, a layout CAD 4 and a parts library 5.

The QSCC database 2 directly stores rules which satisfy the QSCC conceptwhich are extracted by experts in electromagnetic interference problemsthrough experiment, analysis or the like, or the QSCC database 2 storesrules analyzed/extracted by the QSCC designer 3. The libraries (QSCCrules) stored in the QSCC database 2 are constraint conditions which areset when the layout CAD 4 makes layout and wiring design. Asemiconductor LSI or printed circuit board (PCB) designed not to violatethe rules (restrictions) satisfies the requirements of the QSCC rulesand thus realizes electromagnetic interference free design. To bespecific, the QSCC database 2 stores libraries on the allowable maximumwiring length between the QSCC blocks, a line form and the like.

FIG. 2 is a detailed block diagram of the most preferred embodiment ofthe circuit layout design system according to the present invention.Although the block diagram of FIG. 2 shows the system for printedcircuit board (PCB) design, a system for LSI design is basically similarin configuration to the system shown in FIG. 2.

Referring to FIG. 2, the circuit layout design system 1 consists of theQSCC database 2, the QSCC designer 3, the layout CAD 4, the partslibrary 5, a high-rate EMI simulator 6 and a circuit diagram editor 7.

The QSCC designer 3 inputs a net list which indicates the logicconnection of the respective circuit constituent elements and which issupplied from the circuit diagram editor 7 which designs a logiccircuit, an IBIS model and an IMIC model (signal terminal) for eachsemiconductor LSI terminal stored in the parts library 5, and a powersupply model as disclosed in Document 4, and extracts QSCC designconditions so as to group the QSCC on a digital circuit and to giverestrictions to the placement of parts and routing of parts and the likeperformed by the layout CAD 4.

The data extracted by the QSCC designer 3 is stored in the QSCC database2. The QSCC database 2 is connected to the layout CAD 4. The layout CAD4 executes electromagnetic interference free design while referring tothe QSCC database 2, thereby designing the printed circuit board (PCB) 8based on the QSCC concept.

On the other hand, the CAD data designed by the layout CAD 4 istransferred to the high-rate EMI simulator 6 through a specificinterface, and electromagnetic radiation noise is analyzed by thesimulator 6 for final design inspection. Further, it is necessary tomeasure the electric field intensity of the printed circuit board (PCB)8 manufactured using the layout CAD 4 in a qualified radio wave darkroomor an open site so as to determine whether the PCB 8 satisfies theinternational or domestic EMI standard. Therefore, it is effective toanalyze the electromagnetic radiation noise by the high-rate EMIsimulator 6 in advance for real-time inspection for the design.

To extract the power supply model of the semiconductor LSI stored in theparts library 5 (as described in Document 4), there are an extractionmethod by transforming the SPICE model of the LSI itself and anextraction method by measuring the high frequency power supply currentspectrum of the LSI using a magnetic field (current) probe, transformingthe measured spectrum to a time-axis waveform, and thereby constructinga model.

FIG. 3 is a typical view showing one example of grouping overall deviceson the printed circuit board (PCB) 8 to QSCC blocks. In FIG. 3, theminimum unit of the QSCC blocks is an LSI and LISs on the PCB 8 aregrouped according to three frequencies. Referring to FIG. 3, the LSIsare grouped into QSCC blocks 10-1 (high-rate blocks) in the highesthierarchy according to the highest frequency among the three frequenciesusing an algorithm according to the present invention (see FIGS. 7 and 8to be described later). Next, with the resultant QSCC blocks 10-1according to the highest frequency set as units, the LSIs are groupedaccording to the second highest frequency (intermediate-rate frequency)to thereby generate larger QSCC blocks 10-2 than the QSCC blocks 10-1.Finally, with the QSCC blocks 10-2 set as units, the LSIs are groupedaccording to the lowest frequency to thereby generate larger QSCC blocks10-3 than the QSCC blocks 10-2.

In this example, the LSIs are grouped according to the threefrequencies. However, the number of points of analysis frequencies usedfor grouping is not limited to three but may be any arbitrary number.

According to the concept of the quasi-stationary closed circuit (QSCC)stated above, it is obvious that the higher the frequency is, thesmaller the sizes of the QSCC blocks become. In this way, the groupingof the LSIs into the QSCC blocks is executed in a plurality ofhierarchies according to operating frequencies and the grouping iscontinued until all the LSIs mounted on the printed circuit board (PCB)8 are included in one QSCC block.

According to the QSCC theory, there is no electromagnetic radiation fromeach QSCC block and it suffices to consider only electromagneticradiation from the respective lines connecting the QSCC blocks. Due tothis, radiation from each transmission line is analyzed, and the PCB 8is designed based on the restrictions to the layout and wiring design soas to satisfy an EMI standard value with a certain margin, whereby theentire printed circuit board (PCB) 8 free of electromagneticinterference is designed.

Further, the transmission lines are classified to signal wirings andpower supply wirings (noted that the power supply circuit has a defaultto be wired as stated above). The recent study obviously shows that thegreatest cause of the electromagnetic interference derived from digitalequipment lies in the power supply circuit. Therefore, by adopting linecomponents that decrease the impedance of the power supply line in thehigh frequency range as described in the invention (Document 3) of theapplicant of the present application so as to intensify decoupling forthe power supply wirings which are the greatest cause of theelectromagnetic interference, it is possible to efficiently,considerably suppress the electromagnetic interference from the powersupply line. Accordingly, it suffices to execute designing the PCB 8while paying greater attention to the electromagnetic interference fromthe signal wirings.

FIG. 4 is a typical view showing examples of the QSCC blocks. FIG. 4shows a case in which the minimum unit of the QSCC blocks is an LSI.Depending on the operating frequency of the LSI, a QSCC block consistsof one LSI (see FIG. (a)) or a plurality of (two in FIG. 4(b)) LSIs.

FIG. 5 is a typical view showing one example of extending the minimumunits of the QSCC blocks from the LSI to functional blocks in the LSI.It is estimated that if the rate of a semiconductor device is rapidlyaccelerated and shifting to an SOC (System on Chip), then it isdifficult to create QSCC blocks according to the units of the LSIs andit is, therefore, necessary to form QSCC blocks according to smallerunits, i.e., the internal elements of the LSI. Although the drawings andthe description of the specification are centered on the example ofsetting an LSI as the minimum unit of the QSCC blocks, the minimum unitof the QSCC blocks is not limited to the LSI but may be the internalfunctional block of the LSI as shown in FIG. 5.

FIG. 6 shows the concept of a design flow executed by the circuit layoutdesign system according to the present invention. Conventionally, theorganic connection between the process/device design section 11 and thelogic design section 12 has not been established as the integrated EDAsystem and no drastic electromagnetic interference free design ruleshave been, therefore, established.

In the circuit layout design system 1 according to the presentinvention, by contrast, the process design section 11 can be connectedto the logic design section 12 as the integrated EDA system andelectromagnetic interference free design can be realized. In addition,the QSCC designer 3 plays a central role in the circuit layout designsystem 1. The QSCC designer 3 executes layout design and wiring designbased on various QSCC libraries (rules) stored in the QSCC database 2and the high-rate EMI simulator 6 executes real-time inspection andanalysis for the design.

FIG. 7 is a schematic diagram showing an entire QSCC design flow, andFIG. 8 is a schematic diagram showing a design flow executed by the QSCCdesigner 3. The QSCC design flow will first be described. Referring toFIG. 7, a net list is extracted from the logic design data (in a stepS1), and it is searched whether the device (i.e., the QSCC block) isalready registered with the parts library 5 (in a step S2). If it isalready registered (“Yes” in the step S2), it means that rulessatisfying the QSCC requirements exist. Therefore, the processing movesto layout design executed by the layout CAD 4 (a step S5). If the deviceis not registered with the parts library 5 (“No” in the step S2), thedevice is registered as a new device with the library 5 (in a step S3).The processing moves to a step executed by the QSCC designer 3, whichadds QSCC rules (a step S4), and the processing then moves to a stepexecuted by the layout design section (a step S5). The QSCC rulesanalyzed by the QSCC designer 3 are stored in the QSCC database 2 andused as later design information.

Next, the design flow executed by the QSCC designer 3 shown in FIG. 8will be described. Referring to FIG. 8, the basic functions of the QSCCdesigner 3 include a function of grouping the devices into QSCC blocksbased on a certain algorithm, a function of analyzing theelectromagnetic interference of the transmission lines connecting theQSCC blocks, extracting parameters (e.g., a maximum allowable linelength) to be set as CAD design constraint conditions, and registeringthe extracted parameters with the database.

It is noted that FIG. 8 shows an example in which the LSI is a minimumunit of the QSCC blocks. First, an LSI that operates at the highestclock is assumed as the highest class (hierarchy) QSCC (in a step S11).Then, the current waveforms of the wirings between the QSCC blocks areobtained by the SPICE (in a step S12). To obtain a current waveform, thecurrent waveform analyzed by the SPICE is subjected to Fourier transformusing the IBIS model (or IMIC model) (signal terminal) and the NEC powersupply model (power supply terminal) for each terminal of the LSIsstored in the parts library 5, and a current spectrum is obtained.

When the current spectrum is obtained, a field intensity spectrum at adistant location (e.g., at a distance of 10 m) is calculated by dipoleantenna radiation or electromagnetic field analysis (in a step S13).Through this electromagnetic field analysis (transmission lineanalysis), a highly accurate distant field intensity is calculated. Thereason for using the dipole antenna radiation is that normal mode(differential mode) radiation is basically not present or negligiblysmall on an ideal transmission line (e.g., a micro-strip line). This isbecause a current carried across the line also flows as a feedbackcurrent on a flat plane, such as a closest ground layer, with anopposite phase, so that electromagnetic fields cancel each other.However, it does not necessarily mean that 100% of the normal modecurrent returns as the feedback current but only part of the normal modecurrent is transformed to a common mode current, which causes commonmode radiation which is said to dominate the electromagnetic radiation.This is why the electric dipole antenna radiation which can approximatethe common mode radiation is utilized.

Next, it is determined whether the radiation from the line satisfies astandard tolerance (which is an international standard of CISPR22 ITEClass B in the example of FIG. 8) with a certain margin XdB (variable)(in a step S14). If the field intensity spectrum obtained falls withinthe range of ‘tolerance+margin’ (“Yes” in the step S14), an allowablemaximum wiring length between the QSCC blocks is calculated (in a stepS15). The maximum allowable wiring length can be easily calculated basedon the parameters for the dipole antenna radiation. The LSIs can be thusgrouped into the QSCC block in that class. Thereafter, the groupingclass information and the maximum wiring length are stored in the QSCCdatabase 2 (in a step S17).

On the other hand, if the field intensity spectrum does not fall withinthe range of ‘tolerance+margin’ (“No” in the step S14), QSCC groupingscale is reduced. The processing returns to the step S12 and theelectromagnetic field analysis is re-executed (in a step S16). Theprocessing is continued while reducing the QSCC grouping scale until thefield intensity spectrum belongs to one QSCC block in the class.

If grouping in certain classes (in the descending order of hierarchy) iscompleted, it is determined whether all the devices (LSIs) on thecircuit fall within one QSCC block of the QSCC database 2 (in a stepS18). If all the devices belongs to one QSCC block (“Yes” in the stepS18), a signal line structure and a wiring line structure satisfyingQSCC rules for the corresponding class are selected from the partslibrary 5 (in a step S19) and the processing moves to CAD design.

If all the devices, i.e., the entire circuit is not contained in oneQSCC (“No” in the step S18), the QSCC class is degraded by one rank(i.e., a clock frequency is lowered by one rank) and the QSCC block isassumed (in a step S20). In other words, devices are grouped into aplurality of QSCC hierarchies (QSCC classes) according to clockfrequencies. First, the devices are grouped according to the class ofthe highest hierarchy (the highest clock frequency). If the entirecircuit is not contained in one QSCC, grouping is re-executed in ahierarchy (clock frequency) degraded by one rank. The same routine isrepeated until all the devices on the circuit belong to one QSCC.

As already described, there is no radiation from the QSCC blocksthemselves. Due to this, if larger QSCC blocks are sequentiallyconstructed using an algorithm that the radiation of the linesconnecting the QSCC blocks has a certain electromagnetic radiationmargin, the overall printed circuit board is grouped into QSCC blocks asshown in FIG. 3, making it possible to realize consistentelectromagnetic interference free design.

FIG. 9 shows one example of an electric field spectrum as a result ofthe electromagnetic field analysis. FIG. 9 shows the definition of themargin relative to an EMI standard value. Namely, the EMI standard valueshown in FIG. 9 corresponds to the “tolerance” (see the step S14) and“tolerance+margin X” corresponds to a field intensity lower than thisEMI standard value by XdB.

FIG. 10 shows one example of the QSCC database 2. This database 2 is anexample of the database in a case in which an LSI is the minimum unit ofthe QSCC blocks. The QSCC database 2 takes a form of the parts listcreated for the terminals of each LSI and includes QSCC conditionsallocated to each terminal of each LSI. The database 2 is connected tothe layout CAD 4 and the conditions in the database 2 are used by thelayout CAD 4 as those for giving some restrictions to parts placementdesign, wiring design and the like from QSCC viewpoints. In FIG. 10, anexample of allocating an allowable maximum line length, a line form anda line width to each terminal of each LSI is shown. However, theconditions are not limited thereto.

It is noted that a control program shown in the flow charts of FIGS. 7and 8 can be recorded on a recording medium (not shown) in advance andread from the recording medium to an external processor (not shown) andthat the above-stated circuit layout design method can be executed bythe QSCC designer 3, the layout CAD 4, the circuit diagram editor 7 andthe high-rate EMI simulator 6 according to the control program.

INDUSTRIAL APPLICABILITY

The present invention can be utilized for the design of the LSI circuit,the electronic circuit board and the like which are free ofelectromagnetic interference.

1. A circuit layout design method comprising: a quasi-stationary circuitreduction step of dividing an entire circuit represented by a net listand a part library into a plurality of quasi-stationary closed circuitshaving a reduced size so that an intensity of an electromagnetic waveradiated from each of the quasi-stationary closed circuits is not morethan a predetermined value; and a wiring constraint conditioncalculation step of calculating constraint conditions for each ofwirings mutually connecting said plurality of quasi-stationary closedcircuits so that the intensity of the electromagnetic wave radiated fromeach of the wirings is not more than the predetermined value.
 2. Thecircuit layout design method according to claim 1, further comprising: alayout step of laying out parts and the wirings based on said net listand said parts library so as to satisfy said constraint conditions. 3.The circuit layout design method according to claim 1, wherein saidquasi-stationary circuit reduction step and said wiring constraintcondition calculation step are executed for each of frequencies in adescending order and executed so that each of said quasi-stationaryclosed circuits for a certain frequency includes one or more saidquasi-stationary closed circuits for a higher frequency than the certainfrequency.
 4. The circuit layout design method according to claim 1,wherein said constraint conditions include at least a maximum wiringlength.
 5. The circuit layout design method according to claim 1,wherein said quasi-stationary circuit reduction step includes steps of:obtaining a current waveform by a SPICE (a simulation program withintegrated circuit emphasis) using a power supply terminal model and oneof an IBIS (I/O buffer information specification) model and an IMIC (I/Ointerface model for integrated circuit) model; Fourier-transforming saidcurrent waveform to a current spectrum; and calculating a fieldintensity spectrum at a distance by dipole antenna radiation orelectromagnetic analysis using the current spectrum.
 6. The circuitlayout design method according to claim 1, wherein the method is usedfor layout design of a printed circuit board.
 7. The circuit layoutdesign method according to claim 1, wherein the method is used forlayout design of a semiconductor device.
 8. The circuit layout designmethod according to claim 1, wherein the method is used for integrateddesign of a semiconductor device and a printed circuit board.
 9. Acircuit layout design system comprising: quasi-stationary circuitreduction means for dividing an entire circuit represented by a net listand a part library into a plurality of quasi-stationary closed circuitshaving a reduced size so that an intensity of an electromagnetic waveradiated from each of the quasi-stationary closed circuits is not morethan a predetermined value; and wiring constraint condition calculationmeans for calculating constraint conditions for each of wirings mutuallyconnecting said plurality of quasi-stationary closed circuits so thatthe intensity of the electromagnetic wave radiated from each of thewirings is not more than the predetermined value.
 10. The circuit layoutdesign system according to claim 9, further comprising: layout means forlaying out parts and the wirings based on said net list and said partslibrary so as to satisfy said constraint conditions.
 11. The circuitlayout design system according to claim 9 or, wherein saidquasi-stationary circuit reduction means and said wiring constraintcondition calculation means operate for each of frequencies in adescending order and operate so that each of said quasi-stationaryclosed circuits for a certain frequency includes one or more saidquasi-stationary closed circuits for a higher frequency than the certainfrequency.
 12. The circuit layout design system according to any one ofclaims 9 to 11, wherein said constraint conditions include at least amaximum wiring length.
 13. The circuit layout design system according toclaim 9, wherein said quasi-stationary circuit reduction means includes:means for obtaining a current waveform by a SPICE (a simulation programwith integrated circuit emphasis) using a power supply terminal modeland one of an IBIS (I/O buffer information specification) model and anIMIC (I/O interface model for integrated circuit) model; means forFourier-transforming said current waveform to a current spectrum; andmeans for calculating a field intensity spectrum at a distance by dipoleantenna radiation or electromagnetic analysis using the currentspectrum.
 14. The circuit layout design system according to claim 9,wherein the system is used for layout design of a printed circuit board.15. The circuit layout design system according to claim 9, wherein thesystem is used for layout design of a semiconductor device.
 16. Thecircuit layout design system according to claim 9, wherein the system isused for integrated design of a semiconductor device and a printedcircuit board.
 17. A recording medium recording a program for allowing acomputer to execute a circuit layout design method comprising: aquasi-stationary circuit reduction step of dividing an entire circuitrepresented in a net list and a part library into a plurality ofquasi-stationary closed circuits having a reduced size so that anintensity of an electromagnetic wave radiated from each of thequasi-stationary closed circuits is not more than a predetermined value;and a wiring constraint condition calculation step of calculatingconstraint conditions for each of wirings mutually connecting saidplurality of quasi-stationary closed circuits so that the intensity ofthe electromagnetic wave radiated from each of the wirings is not morethan the predetermined value.
 18. The recording medium according toclaim 17, wherein the method further comprises: a layout step of layingout parts and the wirings based on said net list and said parts libraryso as to satisfy said constraint conditions.
 19. The recording mediumaccording to claim 17, wherein in the method, said quasi-stationarycircuit reduction step and said wiring constraint condition calculationstep are executed for each of frequencies in a descending order andexecuted so that each of said quasi-stationary closed circuits for acertain frequency includes one or more said quasi-stationary closedcircuits for a higher frequency than the certain frequency.
 20. Therecording medium according to claim 17, wherein said constraintconditions include at least a maximum wiring length.
 21. The recordingmedium according to claim 17, wherein said quasi-stationary circuitreduction step includes steps of: obtaining a current waveform by aSPICE (a simulation program with integrated circuit emphasis) using apower supply terminal model and one of an IBIS (I/O buffer informationspecification) model and an IMIC (I/O interface model for integratedcircuit) model; Fourier-transforming said current waveform to a currentspectrum; and calculating a field intensity spectrum at a distance bydipole antenna radiation or electromagnetic analysis using the currentspectrum.
 22. The recording medium according to claim 17, wherein themethod is used for layout design of a printed circuit board.
 23. Therecording medium according to claim 17, wherein the method is used forlayout design of a semiconductor device.
 24. The recording mediumaccording to claim 17, wherein the method is used for integrated designof a semiconductor device and a printed circuit board.